1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor memory element such as an EPROM, EEPROM, and or the like.
2. Description of the Related Art
In manufacture of a semiconductor, especially, as a memory (memory element), memory cells are fabricated by repeating lattice patterns to obtain a high-density memory.
For example, an EPROM (Electrically Programmable Read-Only Memory) is manufactured as shown in FIGS. 1 to 5.
As shown in FIG. 1, a predetermined pattern is transferred by photolithography. In FIG. 1, reference numeral 1 indicates a blank pattern, and reference numeral 2 indicates a remaining pattern. In this case, as a resist, a positive-type resist is used. Each of the patterns l is transferred by photolithography and formed to have substantially a single size to obtain a high-density memory cell.
Etching, ion implantation, and oxidization are performed. Element-isolation shown in FIG. 2 is further performed. FIG. 2 is a sectional view along an A-B section in FIG. 1 after the element-isolation is performed.
A gate oxide film, a polysilicon serving as a floating gate, an insulating film, and an electrode serving as a control gate are formed. Thereafter, as shown in FIG. 3, a desired pattern is transferred by photolithography through a mask 31 for forming a gate electrode.
When processes such as etching and ion plantation are performed, a semiconductor memory on which a control gate, a floating gate, a source, and a drain are formed as shown in FIG. 4 is fabricated.
FIG. 4 is a sectional view along a C-D section in FIG. 3. Reference numeral 41 denotes a control gate, reference numeral 42 denotes a floating gate, reference numeral 43 denotes a source, and reference numeral 44 denotes a drain.
Thereafter, processes including film application and photolithography are performed. As shown in FIG. 5, a contact 51 and a metal wiring layer 52 serving as word lines are formed to make it possible to select a cell.
In order to appropriately perform element-isolation, in patterning by photolithography, as shown in FIG. 6, a dimension indicated by reference numeral 63 is a dimension of a control gate. The shapes of the patterns l must be controlled such that the dimension of the lower parts of the control gates are equal to each other.
In a conventional art, these control operations are performed by devising a mask used when a predetermined pattern is transferred.
As shown in FIG. 6, a dimension indicated by reference numeral 61 influences a source line resistance, and a dimension indicated by reference numeral 62 is used for a control gate 65. In this case, when the width indicated by reference numeral 61 decreases, the source line resistance increases. When the width indicated by reference numeral 62 decreases, the control gate comes out of the element-isolation pattern to form a short circuit.
Specific examples of variations in dimension with respect to a focus at dimensions indicated by reference numerals 64 and 61 are shown in FIGS. 7 and 8.
In FIG. 7 showing a variation in dimension with respect to a focus at the dimension indicated by reference numeral 64, for example, it is understood that 0.60 xcexcm or more can be secured as a depth of focus when the dimension is set to be 0.30 xc2x10.02 xcexcm.
As in FIG. 8 showing a variation in dimension for focusing at the dimension indicated by reference numeral 61, when a dimensional gauge of xc2x10.02 xcexcm as in FIG. 7 and a central dimension of 0.31 xcexcm are set, a depth of focus is 0.30 xcexcm. It is understood that the depth of focus at the dimension indicated by reference numeral 61 is half or less of the depth of focus at the dimension indicated by reference numeral 64.
In particular, in FIG. 8, a variable in dimension indicated by reference numeral 61 is large. It is difficult to secure margins to the above-mentioned source line resistance and the control gate and to reduce the dimension.
In an experiment by the present inventor, when simulation which formed a resist pattern by using a conventional mask shown in FIG. 9 was performed, a focus exposure distribution as shown in FIG. 10 was obtained.
In the focus execution distribution, it is understood that as curves in the graph become flat near the center, and as intervals between the curves become small, the mask can cope with a variation in exposure energy and a variation in focus.
As is apparent from the focus exposure distribution in FIG. 10, a depth of focus at a dimension of 0.18xc2x10.04 xcexcm is about 0.40 xcexcm. In general, a depth of focus of 0.1 xcexcm or more is required. It is understood that the dimension easily varies by the variation in process.
When an illuminance distribution from which a finish image of a resist pattern can be supposed was observed, it was understood that the illuminance distribution is high near the central portion and low at upper and lower portions in the longitudinal direction.
The illuminance distribution and the focus exposure distribution can be measured by a simulation device such as PROLITH such that N.A.=0.60 and "sgr"=0.75, and the thickness of a KrF resist is 4200 xc3x85.
As is apparent from the above result, in order to form a resist pattern by using a conventional mask, it is difficult to decrease a variation in dimension with respect to a variation in focus. In addition, the conventional mask has the following problems. That is, desired characteristics cannot be obtained, and the control gate comes out of the element-isolation pattern to make a short circuit.
As described above, it is an object of the present invention to provide a method of manufacturing a semiconductor memory element which can decrease a variation in dimension with respect to a variation in focus.
The object is achieved by the invention described below. More specifically, a first aspect of the invention provides a method of manufacturing a semiconductor memory element including (1) arranging a mask on the upper surface of a semiconductor substrate on which a resist film is formed, (2) using the mask to conduct exposure, (3) using the first, second and third resist patterns to form first, second, and third element-isolation regions, and (4) forming a gate electrode. With respect to arranging a mask, the mask has first, second and third rectangular patterns. The first rectangular pattern has a first direction as a longitudinal direction thereof. The second rectangular pattern is arranged apart from the first pattern in the first direction and has the first direction as a longitudinal direction thereof. The third rectangular pattern is arranged apart from the first and second patterns in a second direction intersecting the first direction and has the first direction as a longitudinal direction thereof. Further the mask has an auxiliary pattern extending in the first direction. The auxiliary pattern is made on each central portion of the first, second, and third patterns on the upper surface of the semiconductor substrate. Forming first, second, and third resist patterns on the resist film follows exposing with the mask. The first to third resist patterns correspond to the first to third patterns on the mask. With respect to forming first to third element-isolation regions with the first to third resist patterns on the semiconductor substrate surface, these element-isolation regions respectively correspond to the first to third resist patterns. The gate electrode extends in the second direction. The gate electrode is formed from the upper surface of the first element-isolation region to the upper surface of the third element-isolation region through an area between the first and third element-isolation regions. Further, the gate element-isolation region is formed from the upper surface of the second element-isolation region to the upper surface of the third element-isolation region through an area between the second and third element-isolation regions.
In the method, the sizes of the first, second, and third patterns may be almost equal to each other.
In the method, the auxiliary pattern may decrease light intensities of the central portions of the first, second, and third patterns.
In the method, the auxiliary pattern may be a rectangular pattern and has the first direction as a longitudinal direction.
In the method, an electrically programmable read-only memory may be used.
In the method, a width of the gate electrode in the first direction may be 0.2 xcexcm or less.
In the method, dimensions of the central portions of the first, second, and third patterns in the second direction may be longer than dimensions of both the end portions of the first, second, and third patterns in the second direction.
In the method, correction patterns respectively including the four corners of the first, second, third patterns may be arranged on the first, second, and third patterns.
According to a second aspect of the invention, in the step of arranging a mask in the method of manufacturing a semiconductor memory element of the first aspect, a mask which has a common first pattern, a common second pattern, the first and second patterns, and a third pattern and in which a plurality of auxiliary patterns respectively extend on the first, second, and third patterns, in the second direction and are arranged such that adjacent intervals in the first direction between the auxiliary patterns become smaller toward the central portions of the patterns is used. The step of forming first, second, and third resist patterns on a resist film, the step of forming first, second, and third element-isolation regions on a semiconductor substrate surface, and the step of forming gate electrodes are the same as those in the method of the first aspect.
In the method of the second aspect, sizes of the first, second, and third patterns may be almost equal to each other.
In the method of the second aspect, the auxiliary patterns may decrease light intensities of the central portions of the first, second, and third patterns.
In the method of the second aspect, an electrically programmable read-only memory may be used.
In the method of the second aspect, a width of the gate electrode in the first direction may be 0.2 xcexcm or less.
In the method of the second aspect, dimensions of the central portions of the first, second, and third patterns in the second direction may be longer than dimensions of both the end portions of the first, second, and third patterns in the second direction.
In the method of the second aspect, correction patterns respectively including the four corners of the first, second, third patterns may be arranged on the first, second, and third patterns.